`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2020/11/02 20:15:48
// Design Name: 
// Module Name: add_8_8
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module add_8_8(
    output [7:0] sum,
    output carry,
    input [7:0] num1,
    input [7:0] num2
    );
    
    wire carry_internal[8:0];
    
    add_1_1 add0(sum[0], carry_internal[0], num1[0], num2[0], 0);
    add_1_1 add1(sum[1], carry_internal[1], num1[1], num2[1], carry_internal[0]);
    add_1_1 add2(sum[2], carry_internal[2], num1[2], num2[2], carry_internal[1]);
    add_1_1 add3(sum[3], carry_internal[3], num1[3], num2[3], carry_internal[2]);
    add_1_1 add4(sum[4], carry_internal[4], num1[4], num2[4], carry_internal[3]);
    add_1_1 add5(sum[5], carry_internal[5], num1[5], num2[5], carry_internal[4]);
    add_1_1 add6(sum[6], carry_internal[6], num1[6], num2[6], carry_internal[5]);
    add_1_1 add7(sum[7], carry_internal[7], num1[7], num2[7], carry_internal[6]);
    
    assign carry = carry_internal[7];
    
endmodule
